1. Field of the Invention
The present invention relates to memories. More specifically, the present invention relates to low power, high speed, digital computer memories.
2. Description of the Related Art
Modern computing devices utilize a variety of kinds of memory devices to store and access information. Several memory device technologies are familiar to those skilled in the art and include the general classes of random access memories (“RAM”) and read only memories (ROM”). These classes further comprise static RAM (“SRAM”), dynamic RAM (“DRAM”), programmable ROM (“PROM”), erasable PROM (“EPROM”), electrically erasable PROM (“EEPROM”), as well as FLASH memory, and other memory types known to those skilled in the art. Most memory devices employ an internal architecture in the form of an array memory of bit cells, comprised of plural rows and plural intersecting columns. This architecture is beneficial in allowing random access to the memory, and in minimizing the number of circuit components needed to implement any given memory size. A memory bit cell is placed at each intersecting row and column in the array. Typically, a particular memory bit cell is accessed by activating its row and then reading or writing the state of its column. Memory sizes are defined by the row and column architecture. For example, a 1024 row by 1024 column memory array defines a memory device having one megabit of memory cells. The memory bit cells are often times arranged into logical groups of memory bits, called words. A convention has emerged in the art, where the array rows are referred to as word lines and the memory columns referred to as bit lines.
Two important, and limiting, characteristics of memory devices are current, or power, consumption and access speed. Power consumption is particularly important in portable battery powered devices. Access speed is important in all devices where designers seek increased performance and functions within computing devices. These two characteristics are fundamentally opposed to one anther in that the faster a memory device is operated, the more power it consumes. Power consumption in memory devices was significantly reduced with the deployment of metal oxide semiconductor transistors (“MOS”) and complementary MOS (“CMOS”) devices.
A CMOS device advantageously utilizes a complementary pair of insulated gate field effect transistors as a switching circuit such that in a quiescent state, at least one of the two transistors is switched fully off with the gate input signals insulated from the drain-source channels by a metal oxide. As such, no current flows through the insulated gate inputs. Since at least one of the drain-source junctions is pinched off in the quiescent state, no current flows though the drain-source paths either. However, when the device is transitioned from a first “on” state” to a second “off” state, the drain-source junctions of each transistor transition through the active region of the transistors, and a small amount of current is therefore consumed. Even in a memory that does not switch active devices at the bit cell junctions, such as a DRAM, a change in voltage within the circuit must act across the capacitive load of the circuit. As is known to those skilled in the art, changing the voltage in a reactive circuit (inductive or capacitive) results in the movement of current in that circuit. Current flow, or power consumption, in capacitive circuit is quantified as the circuit capacitance multiplied by the first derivative of the change in voltage with respect to time. Thus, power consumption in the active state of switching a CMOS device, or any capacitive memory device, can be limited by reducing the circuit capacitance.
Memory devices are most commonly implemented as semiconductor integrated circuits. These circuits are know to those skilled in the art and are comprised of active doped semiconductor circuit devices, such as diodes and transistors, interconnected with metallic traces. Resistive, capacitive, and even inductive components can also be formed using integrated circuit technology. Multiple layers of circuitry are built up upon one another, separated with non-doped insulating layers. In memory devices organized in the aforementioned array structure, the word-rows and bit-columns are formed with long metallic traces that are tapped at each array junction, where a memory bit cell is formed.
The trend in semiconductor memory devices has been toward higher circuit density with higher numbers of bit cells per device, lower operating voltages, and higher access speeds. What this has resulted in, at the physical device level, is smaller device dimensions and closer metallic traces spacing. Modern devices now implement 0.13 micron drain-source channel lengths, and metallic traces about 0.18 microns wide and spaced about 0.16 microns from one another. As will be appreciated by those skilled in the art, the combination of longer trace lengths combined with the close row and column trace spacing results in a limit of operative speed due to the capacitive loads that must be switch with each memory access. In fact, the power consumed by the memory array switching actions is the single greatest current demand in many computing devices. The problem is exacerbated by the reduced circuit dimensions because the reduced current sourcing ability of such small devices, especially taken in combination with the large number of bit cells that are activated with each word row access. In effect, a smaller switch must now control a larger load.
The close spacing of metallic row and column traces with one another and the device ground plane contribute to relatively high capacitive loads and the time constraints that such loads place upon switching and current consumption. They also contribute to significant capacitive coupling between adjacent traces. This coupling is a manifestation of noise that also limits device performance due to signal cross-talk that interferes with the ability of certain sensing circuitry to reliably detect a present output state of switching components within the memory. Thus, there is a need in the art to reduce power consumption, reduce the magnitude of capacitive loads within memory arrays, and reduce the noise coupling within memory devices while reading and writing data thereto.